SiGe FinFET has been explored for its benefit of high current drivability provided by channel strain [1-5]. We have demonstrated SiGe CMOS FinFET at 10nm technology ground rules including epitaxial defectivity control, DC performance and reliability benefit [6-8]. One concern of SiGe FinFET is channel strain relaxation by fin cut process  inducing local layout effect (LLE), which is crucial for product design. In this paper, we thoroughly examined LLE in SiGe pFinFET and explored its mitigation techniques. Two techniques are proposed and demonstrated successful LLE mitigation, which drives forward SiGe FinFET insertion to technology.