Novel enhanced stressor with graded embedded SiGe source/drain for high performance CMOS devices

Abstract

We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled a pFET performance gain of 15% over a nongraded eSiGe control. When combined with a compressive stress liner (CSL), the pFET drive current reached 770μA/μm at Ioff=100nA/μm with VDD=1V. Competitive nFET performance was maintained. Parasitics such as suicide and junction characteristics were not degraded.