High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
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16 results for H. Utomo
(110) Channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (R ext) engineering
- B. Yang
- A. Waite
- et al.
- 2007
- IEDM 2007
Novel enhanced stressor with graded embedded SiGe source/drain for high performance CMOS devices
- J.-P. Han
- H. Utomo
- et al.
- 2006
- IEDM 2006
Process Challenge in Analog Computing Hardware using Phase Change Memory (PCM)
- Victor Chan
- I. Ok
- et al.
- 2023
- ASMC 2023
A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM
- Nanbo Gong
- W. Chien
- et al.
- 2020
- VLSI Technology 2020
Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
- K. Cheng
- S.-C. Seo
- et al.
- 2014
- VLSI Technology 2014
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
Channel Strain Characterization in Embedded SiGe by Nano-beam Diffraction
- J. Li
- A. Lamberti
- et al.
- 2008
- ECS Meeting 2008
Higher hole mobility induced by twisted Direct Silicon Bonding (DSB)
- M. Hamaguchi
- H. Yin
- et al.
- 2008
- VLSI Technology 2008
High performance transistors featured in an aggressively scaled 45nm bulk CMOS technology
- Z. Luo
- N. Rovedo
- et al.
- 2007
- VLSI Technology 2007