Fully depleted SOI (FDSOI) is a viable option for continued CMOS scaling. In this paper, we overview key challenges for designing and manufacturing extremely thin SOI (ETSOI) devices and provide solutions to each challenge. We demonstrate successful fabrication of ETSOI devices with physical gate length down to 25nm and SOI channel thickness down to 3.5nm. Our highly scaled ETSOI devices exhibit excellent electrostatics and respectable performances. We further discuss unique opportunities enabled by ETSOI for reducing CMOS process complexity and therefore reducing process cost, which in turn at least partially offsets the higher cost of SOI substrates. The unique advantages of ETSOI in conjunction with the presented solutions to challenges render ETSOI a strong candidate for scaling planar CMOS to 22-nm node and beyond. ©The Electrochemical Society.