An ultrafast (10-μs delay) measurement technique is used to characterize ac negative-bias temperature instability-induced threshold voltage shift (Δ VT) in replacement metal-gate-based high-K metal gate Si and SiGe p-FinFETs. Time kinetics of stress and recovery, voltage acceleration factor, temperature activation energy (EA), frequency (f), and pulse duty cycle (PDC) dependence are shown for different germanium percentages (Ge%) in the channel and nitrogen percentages (N%) in the gate insulator. A comprehensive physical model framework based on uncorrelated contributions from interface (Δ VIT) and bulk oxide (Δ VOT) trap generation and hole trapping in preexisting defects (Δ VHT) is used to explain the measured data at different stress biases (VGSTR), temperatures (T), f, and PDCs. Direct-current I-V measurements are used to independently verify the interface-trap generation component for ac stress. End-of-life degradation for different processes under dc and ac conditions is estimated by using the calibrated model and compared to predictions from conventional analytical methods.