Matthias Brändli

Title

Digital Circuit Design

Publications

A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS
- - Lukas Kull
  - Thomas Toifl
  - et al.
- 2014
- ISSCC 2014
A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm² at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS
- - Toke Meyer Andersen
  - Florian Krismer
  - et al.
- 2014
- ISSCC 2014
A 3.1 mW 8b 1.2 GS/s single-Channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS
- - Lukas Kull
  - Thomas Toifl
  - et al.
- 2013
- IEEE JSSC
A 10 Gb/s 8-tap 6b 2-PAM/4-PAM tomlinson-harashima precoding transmitter for future memory-link applications in 22-nm SOI CMOS
- - Marcel Kossel
  - Thomas Toifl
  - et al.
- 2013
- IEEE JSSC
A 16Gb/s 3.7mW/Gb/s 8-tap DFE receiver and baud rate CDR with 30kppm tracking bandwidth
- - Pier Andrea Francese
  - Thomas Toifl
  - et al.
- 2013
- A-SSCC 2013
A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS
- - Lukas Kull
  - Thomas Toifl
  - et al.
- 2013
- VLSI Circuits 2013
A 4.6W/mm² power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS
- - Toke M. Andersen
  - Florian Krismer
  - et al.
- 2013
- APEC 2013
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS
- - Lukas Kull
  - Thomas Toifl
  - et al.
- 2013
- ISSCC 2013
Room-temperature THz imaging based on antenna-coupled MOSFET bolometer
- - Thomas Morf
  - Bernhard Klein
  - et al.
- 2013
- MEMS 2013
Design of a wide-bandwidth on-chip antenna for uncooled passive THz imaging
- - Bernhard Klein
  - Thomas Morf
  - et al.
- 2013
- iWAT 2013

Patents

- 16 Sep 2024
- US
- 12095473
Time Domain Interleaving
- 13 Nov 2023
- US
- 11816062
Control Unit For Qubits
- 05 Jul 2021
- US
- 11057039
Clock Divider With Quadrature Error Correction
- 14 Nov 2016
- US
- 9496008
Determination Of A Common Mode Voltage

Projects

High-Speed I/O Links
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.

Top collaborators

Thomas Morf

Senior Research Scientist

Pier Andrea Francese

Principal RSM - Analog Circuit Design

Marcel Kossel

Circuit Designer

Cezar Zota

Staff Research Scientist, Master inventor