A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
- John F. Bulzacchelli
- Christian Menolfi
- et al.
- 2012
- IEEE JSSC
Matthias Brändli
Title
Digital Circuit Design
Publications
A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS
- Thomas Toifl
- Michael Ruegg
- et al.
- 2012
- VLSI Circuits 2012
A 2.6 mW/Gbps 12.5 Gbps RX with 8-Tap switched-capacitor DFE in 32 nm CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
A 2.6mW/Gbps 12.5Gbps RX with 8-tap switched-cap DFE in 32nm CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2011
- VLSI Circuits 2011
A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI
- Christian Menolfi
- Thomas Toifl
- et al.
- 2011
- ISSCC 2011
Patents
- US
- 12095473
- US
- 11816062
- US
- 11057039
- US
- 9496008
Projects
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.
Top collaborators
TM
Thomas Morf
Senior Research Scientist
PF
Pier Andrea Francese
Principal RSM - Analog Circuit Design
MK
Marcel Kossel
Circuit Designer
CZ
Cezar Zota
Staff Research Scientist, Master inventor