ISSCC 2014
Conference paper

A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS

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Forthcoming optical communication standards such as ITU OTU-4 and 100/400Gb/s Ethernet require ADCs with more than 50GS/s and at least 5 ENOB to enable complex equalization in the digital domain. SAR ADCs and interleaved ADCs made impressive progress in recent years. First CMOS ADCs with at least 6b and conversion rates exceeding 20GS/s were presented [1-3], proving that interleaved SAR ADCs are an optimal choice for high-speed ADCs with moderate resolution. We present an interleaved CMOS ADC architecture based on an asynchronous redundant SAR ADC core element. It was measured up to a sampling rate of 100GS/s and can be operated from a single supply voltage. At 90GS/s, the measured SNDR stays above 36.0dB SNDR up to 6.1GHz and 33.0dB up to 19.9GHz input frequency while consuming 667mW. The ADC is implemented in 32nm digital SOI CMOS and occupies 0.45mm2. © 2014 IEEE.