VLSI Circuits 2013
Conference paper

A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS


An asynchronous 8× interleaved redundant SAR ADC achieving 8.8GS/s at 35mWand 1V supply is presented. The ADC features pass-gate selection clocking scheme for time-skew minimization and per-channel gain control based on low-power reference voltage buffers. The sub-ADC stacks the capacitive SAR DAC (CDAC) with the reference capacitor to reduce the area and enhance the settling speed. It achieves 38.5dB SNDR and 58fJ/conversion-step with a core chip area of 0.025mm2 in 32nmCMOS SOI technology. © 2013 JSAP.