A-SSCC 2013
Conference paper

A 16Gb/s 3.7mW/Gb/s 8-tap DFE receiver and baud rate CDR with 30kppm tracking bandwidth

View publication


The circuit presented is a power-efficient implementation of a 16 Gb/s I/O link NRZ receiver in 22 nm CMOS SOI. A CTLE feeds an 8-tap DFE for ISI equalization. The first tap uses digital speculation and the following seven taps are realized with switched-capacitor technique. Timing recovery and control are performed with a Mueller-Müller type-A baud rate CDR. The receiver architecture is half rate and requires only a single phase rotator. In total, six comparators in each even/odd signal path slice recover both data and timing information. The timing information extraction requires four additional comparators per slice in parallel to the two required by the first-tap DFE speculation. The CDR digital section operates at quarter rate and features a low-latency implementation for the timing control loop. At 16 Gb/s, 1 Vppd PRBS31 data transmitted without FFE equalization are recovered error-free (BER < 10-12) across a PCB channel with 34 dB attenuation at 8 GHz. The measured tracking bandwidth is 30 kppm (16 GHz ±480 MHz), and an amplitude of 3 UIPP is tolerated at 1 MHz sinusoidal jitter. The sinusoidal jitter amplitude tolerance measured at 10 Gb/s is 0.4 UIPP at 10 MHz and remains above 0.2 UIPP up to 1 GHz with PRBS31 data recovered error-free (BER< 10-12) across a PCB channel with 27 dB attenuation at 5 GHz. The power efficiency is 3.7 mW/Gb/s, including the full-rate clock receiver. © 2013 IEEE.