ISSCC 2013
Conference paper

A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS

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Next-generation digital high-speed links require fast, yet energy-efficient ADCs at minimum area. Recent years saw impressive progress in SAR ADC designs towards higher sampling speed. Asynchronous clocking [2-5], redundant capacitive DACs (CDAC) [2], multi-bit decisions per step [1,3-4] and interleaved designs [2-3] have been presented. We present an asynchronous redundant single-channel ADC achieving 1.2GS/s at 1V supply by using two comparators in alternation to relax comparator reset timing. The ADC achieves 39.3dB SNDR and 34fJ/conversion-step with a core chip area of 0.0015mm2. © 2013 IEEE.