Matthias Brändli

Title

Digital Circuit Design

Publications

A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET
- - Danny Luu
  - Lukas Kull
  - et al.
- 2017
- VLSI Circuits 2017
A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET
- - Lukas Kull
  - Danny Luu
  - et al.
- 2017
- ISSCC 2017
A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET
- - Alessandro Cevrero
  - Ilter Ozkaya
  - et al.
- 2017
- ISSCC 2017
Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters
- - Toke M. Andersen
  - Florian Krismer
  - et al.
- 2017
- IEEE-TEPL
A 10 W On-Chip Switched Capacitor Voltage Regulator with Feedforward Regulation Capability for Granular Microprocessor Power Delivery
- - Toke M. Andersen
  - Florian Krismer
  - et al.
- 2017
- IEEE-TEPL
CMOS ADCs Towards 100 GS/s and beyond
- - Lukas Kull
  - Danny Luu
  - et al.
- 2016
- CSICS 2016
Feedback delay reduction of Tomlinson- Harashima precoder in 14 nm CMOS via pipelined MAC units operated entirely with CSA arithmetic
- - Marcel Kossel
  - Matthias Braendli
  - et al.
- 2016
- Electronics Letters
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS
- - Hazar Yueksel
  - Matthias Braendli
  - et al.
- 2016
- ESSCIRC 2016
Design considerations for 50G+ backplane links
- - Thomas Toifl
  - Matthias Braendli
  - et al.
- 2016
- ESSCIRC 2016
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS
- - Lukas Kull
  - J. Pliva
  - et al.
- 2016
- IEEE JSSC

Patents

- 16 Sep 2024
- US
- 12095473
Time Domain Interleaving
- 13 Nov 2023
- US
- 11816062
Control Unit For Qubits
- 05 Jul 2021
- US
- 11057039
Clock Divider With Quadrature Error Correction
- 14 Nov 2016
- US
- 9496008
Determination Of A Common Mode Voltage

Projects

High-Speed I/O Links
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.

Top collaborators

Thomas Morf

Senior Research Scientist

Pier Andrea Francese

Principal RSM - Analog Circuit Design

Marcel Kossel

Circuit Designer

Cezar Zota

Staff Research Scientist, Master inventor