Lukas Kull, Danny Luu, et al.
ISSCC 2017
We report a 5Gb/s data link implemented in 14nm FinFET CMOS SOI technology in which a single transmitter (TX) broadcasts NRZ data to eight receivers (RXs) distributed along an on-chip RC-dominated 10mm-long channel. The TX comprises a full-rate AC-coupled 2-tap FIR driver with a quarter-rate pre-driver. Each RX is equipped with a novel decision-gated 1-tap speculative DFE optimized for low-power. The RX architecture is half-rate and sliced data are de-multiplexed at quarter-rate. PRBS generator and checker are available on-chip. Correct operation was verified with PRBS31 data transmitted at 5Gb/s and concurrently received error-free at each drop with >40% horizontal margin (BER<10-12). At this data-rate the efficiency is 7.1fJ/b/mm' resulting in the best performance among multi-drop on-chip data links so far published (to the best of our knowledge). The TX and eight RXs are running on a 0.5 V power supply and consume 0.62 and 0.98mW' respectively.
Lukas Kull, Danny Luu, et al.
ISSCC 2017
Alessandro Cevrero, Ilter Ozkaya, et al.
ISSCC 2019
Ilter Ozkaya, Alessandro Cevrero, et al.
IEEE JSSC
Marcel Kossel, Christian Menolfi, et al.
ESSCIRC 2017