ISSCC 2017
Conference paper

A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET

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The rapid increase of bandwidth requirements between processors in high-end servers motivates the integration of optical interconnects on the first-level processor package [1]. In this perspective, additional bandwidth density can be achieved by integrating optical transceivers directly into the processor die. Optically enabled CPUs can provide energy-efficient, low-latency interconnects over long distances (>10m) in future data-centers. Integrated photonic interconnect technology will require sensitive and low-power receiver (RX) circuits that operate at high data rates.