Publication
IEEE-TEPL
Paper

Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters

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Abstract

The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter operation and efficiency into account. This paper extends an existing SC state space modeling framework to include the bottom plate capacitor. The developed model is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter. Implemented in a 32 nm SOI CMOS technology that features the high-density deep trench capacitor, the on-chip converter achieves 86% maximum efficiency at 4.6W/mm2 power density while converting from a 1.8 V input voltage to 830 mV output voltage.

Date

01 Jan 2017

Publication

IEEE-TEPL

Authors

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