Publication
ESSCIRC 2016
Conference paper

Design considerations for 50G+ backplane links

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Abstract

The constantly increasing need for I/O bandwidth push electrical backplane links to data rates of 50Gb/s and above. Although board materials have improved significantly, backplane links are increasingly limited by signal attenuation while suffering from ISI, jitter, device noise and cross-talk. In this paper we summarize these limitations, and show possible directions to cope with them in order to further extend the achievable data rate.

Date

18 Oct 2016

Publication

ESSCIRC 2016

Authors

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