Publication
ISSCC 2017
Conference paper

A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET

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Abstract

High-speed SAR ADCs became popular with modern CMOS technologies because of their mostly digital logic, making them highly suitable for compact and power-efficient multi-GS/s time-interleaved ADCs. As many applications cannot tolerate input swings ≥1Vppd, comparator noise limits the SNDR of SAR ADCs, making gain stages necessary for higher SNDR - either as comparator pre-amplifiers or between pipelined stages. Pre-amplifiers significantly reduce the conversion speed of the ADC, but they provide maximum SNDR because linearity of the amplifier is irrelevant. An interstage amplifier for pipelining best suits mid-resolution SAR ADCs, where the required linearity is limited. Moreover, pipelining results in higher conversion speeds and power efficiency because the gain stage is used only once per conversion [1]. This work presents a pipelined-SAR ADC architecture that exceeds the conversion speed of previous pipelined and single-stage SAR ADCs. The ADC achieves 50dB SNDR and 950MS/s at 2.26mW, and 1.5GS/s at 6.92mW on an area of 0.0016mm2.

Date

02 Mar 2017

Publication

ISSCC 2017

Authors

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