A 6+ GHz 128KB Multi-Port L1 Cache using Ground Rule Clean 10T Bitcells in 5nm Technology
- Rajiv Joshi
- John Davis
- et al.
- 2025
- VLSI Technology and Circuits 2025
Publications
14 results for Design and Enablement
Fast And Accurate Machine Learning Prediction of Back-End-Of-Line Thermal Resistances in Backside Power Delivery and Chiplet Architectures
- Prabudhya Roy Chowdhury
- Aakrati Jain
- et al.
- 2025
- ECTC 2025
Diagnosing and Prioritizing Issues in Automated Order-Taking Systems: A Machine-Assisted Error Discovery Approach
- Maeda Hanafi
- Frederick Reiss
- et al.
- 2025
- CHI 2025
Multi-reticle stitching: Applications from packaging to High-NA EUV
- Chris Bottoms
- Rick Johnson
- et al.
- 2025
- SPIE Advanced Lithography + Patterning 2025
IBM Telum II: Next Generation 5.5GHz Microprocessor with On-Die Data Processing Unit and Improved AI Accelerator
- Gerry Strevig
- Chris Berry
- et al.
- 2025
- ISSCC 2025
Touch Temperature Safety Standards and their Impact on Server Design
- Milnes David
- Felipe Valenzuela
- et al.
- 2024
- ITherm 2024
Artifical Intelligence Governed Processor
- Alper Buyuktosunoglu
- David Trilla Rodriguez
- 2024
- ISCA 2024
Unitxt: Flexible, Shareable and Reusable Data Preparation and Evaluation for Generative AI
- Elron Bandel
- Yotam Perlitz
- et al.
- 2024
- NAACL 2024
Cloud bursting an EDA workload with ML-driven technique for future SoC development
- Wachirawit Ponghiran
- Jinwook Jung
- 2024
- VLSI Technology and Circuits 2024
The role of interface design on prompt-mediated creativity in Generative AI
- Maddalena Torricelli
- Mauro Martino
- et al.
- 2024
- WebSci 2024