IBM Telum II: Next Generation 5.5GHz Microprocessor with On-Die Data Processing Unit and Improved AI Accelerator

Abstract

The IBM Z microprocessor, Telum II, has been redesigned for the zNext system to improve performance and system capacity over the previous z16 system [1]. The system topology consists of four Dual-Chip Modules (DCM) each composed of two central-processor (CP) chips per drawer. The system can be configured with up to four drawers and a total of 32 CP chips in a fully coherent shared memory system. Key system capacity and performance improvements came from enhancements to the core and the increased cache size. Telum II increases the number of L2 cache instances from 8 to 10 and uses Samsung’s high-density SRAM cell to grow the L2 cache by 40% from 32MB on Telum to 36MB per L2 cache instance. Each processor core and the DPU have a private 36MB L2 cache along with an extra floating L2 which are fully connected by a 352 GB/s ring. The on-chip shared virtual L3 cache increases from 256MB to 360MB.