Multi-reticle stitching: Applications from packaging to High-NA EUV

Abstract

Large-format chips and interposers are a necessity in tailored applications where fast and high-bandwidth communication between a large number of computing or memory cores is critical. This is especially true for AI, server, optics, and quantum applications. Chips with distinct designs that are larger than a single exposure field require the use of multi-reticle stitching to achieve a cohesive circuit. This study provides an overview of multi-reticle stitching techniques from the standpoint of mask design, process, and characterization. Through the analysis of stitch process data from i-line, DUV, and EUV we probe the costs and benefits associated with multi-reticle stitching, the co-optimization of stitching and layer to layer overlay performance, and provide specifications for robust process designs that utilize stitching.