3D Die-Stack on Substrate (3D-DSS) Packaging Technology and FEM Analysis for 55um-75um Mixed Pitch Interconnections on High Density Laminate Katsuyuki SakumaMukta Farooqet al.2021ECTC 2021
Plating-free Bumping by Cu Nanopaste and Injection Molded Solder (IMS) for Fine Pitch Flip Chip JoiningToyohiro AokiEiji Nakamuraet al.2020ECTC 2020
Proposal of Package Structure Requirements for Effective Cooling from the Bottom Side of Chips (from the Substrate Side), Aiming for a Three-Dimensional (3D) Chip StackKeiji MatsumotoHiroyuki Mori2016ECTC 2016
D2W and W2W Hybrid bonding system with below 2.5 micron pitch for 3D chiplet AI applicationsKatsuyuki SakumaRoy Yuet al.2024IEDM 2024
Design of Analog-AI Hardware Accelerators for Transformer-based Language Models (Invited)Geoffrey BurrSidney Tsaiet al.2023IEDM 2023
Optical Communication and Energy Conversion for Small-Footprint Edge ComputingNing Li2020MRS Spring/Fall Meeting 2020
Artificial Intelligence (AI) based methodology to minimize asymmetric bare substrate warpageSathya RaghavanHiroyuki Moriet al.2023ECTC 2023
Towards a Formally Verified Security Monitor for VM-based Confidential ComputingWojciech OzgaGuerney Huntet al.2023MICRO 2023
A NRZ/PAM4 SST TX in 5nm FinFET CMOS with 3-tap FFE and 0.7pJ/b efficiency at 100 Gb/s PAM4Marcel KosselMatthias Brandliet al.2024ESSERC 2024