Publication
S3S 2015
Conference paper

Essential edge protection techniques for successful multi-wafer stacking

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Abstract

For applications such as stacked DRAM on logic, 3D die-on-wafer or die-on-die approaches with multiple stacked chips have shown vast improvement in bandwidth while also reducing power consumption [1]. The benefit of chip level stacking can be further enhanced by progressing to wafer-scale bonding. Wafer level integration with through-silicon-vias (TSVs) offers lower production costs, much higher density of interconnects, and better bonding overlay accuracy when compared to chip level processing [2]. However, to take full advantage of the benefits of wafer-to-wafer integration, wafer edge quality must be optimized to suppress bonding voids at the wafer edge. Bonding voids can lead to delamination and subsequent detachment of transferred layers, thereby preventing further processing of wafers due to potential tool contamination with particulates or exposed underlying Cu pattern. For true multi-wafer stacking, with greater than two strata, edge quality, as defined by topography and uniformity of films, becomes essential for multi-stacking success and yield. Prior work on wafer level multi-stacking [3] with low-temperature oxide bonding and copper TSVs has been demonstrated with up to 4-strata [Fig 1]. In order to achieve consistent results for large stacks, lithographic and copper edge bead removal processes (EBR) must be precisely tuned to prevent undesirable wafer edge topography during BEOL processing. This abstract reports the first use of wafer edge pattern protection for tool agnostic edge processing by incorporating a narrow pattern-free buffer zone at the wafer edge to enable a large process window for general tool sets not optimized for far edge processing. Alternate protection schemes for wafer stacking have targeted bevel or edge protection during handle removal/thinning [4]. Multiple edge protection schemes may be necessary to preserve edge quality. The key feature of this work focuses on pattern protection at the wafer top surface near the bevel, where voids in patterned regions are most prevalent in an otherwise void-free wafer. By incorporating a double patterning scheme for thick BEOL metal layers, which utilizes a standard maskless lithographic wafer edge exposure module, edge protection has been shown to vastly diminish edge voids, improve CMP uniformity, and provide a robust means to multi-wafer stacking.

Date

20 Nov 2015

Publication

S3S 2015

Authors

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