2.1D packaging is a potential low cost alternative to 2.5D packaging. Instead of using silicon/glass interposers, in 2.1D package, a high-density wiring layer is on the chip side of the substrate acting as an interposer. One of the challenges for 2.1D packaging is the thermal deformation of organic substrates due to their highly asymmetric structure. In this report, we analyzed the thermal warpage of 2.1D substrates by finite element method. The analyses are done on a 3-2-3 build-up layer structure with high-density wiring layers on the chip mounting side, since it has potential applications as multi-chip package products. The analysis showed that the warpage of the test substrate is 250μm for the substrate of 47.5mm×47.5mm in size. The adjustment of the Cu loading ratio of the back build-up layers only reduces the warpage by 17%. We propose a structure in which a circuitry layer and an insulating via layer are added to the back side of the substrate for the warpage reduction. The thickness of the circuitry layer is set equal to the total thickness of the high density circuitry layers. The thickness of via layer is also set equal to the total thickness of the insulating layers between the high-density wiring layers. However we found that the optimum Cu loading ratio for the adjustment circuitry layer is lower than the average Cu loading ratio for the high-density wiring layers by 20 to 40 %. The analysis showed that the proposed substrate structure reduces the warpage significantly.