Prospects of high-Ge-content strained SiGe for advanced FinFET generations
- Pouya Hashemi
- Karthik Balakrishnan
- et al.
- 2016
- PRiME/ECS Meeting 2016
Publications
This is our catalog of publications authored by IBM researchers, in collaboration with the global research community. It’s an ever-growing body of work that shows why IBM is one of the most important contributors to modern computing.
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35 results for Renee Mo
Demonstration of record SiGe transconductance and short-channel current drive in High-Ge-Content SiGe PMOS FinFETs with improved junction and scaled EOT
- Pouya Hashemi
- Kam-Leung Lee
- et al.
- 2016
- VLSI Technology 2016
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
- Dechao Guo
- G. Karve
- et al.
- 2016
- VLSI Technology 2016
Replacement high-K/metal-gate High-Ge-content strained SiGe FinFETs with high hole mobility and excellent SS and reliability at aggressive EOT ∼7Å and scaled dimensions down to sub-4nm fin widths
- Pouya Hashemi
- Takashi Ando
- et al.
- 2016
- VLSI Technology 2016
SiGe-on-insulator symmetric lateral bipolar transistors
- Jeng-Bang Yau
- Jin Cai
- et al.
- 2015
- S3S 2015
High-mobility high-Ge-content Si1-xGex-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x∼ 0.7, scaled EOT∼8.5Å and ∼10nm fin width
- Pouya Hashemi
- Takashi Ando
- et al.
- 2015
- VLSI Circuits 2015
High-mobility High-Ge-Content Si1-xGex-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x∼ 0.7, scaled EOT∼8.5Å and ∼10nm fin width
- Pouya Hashemi
- Takashi Ando
- et al.
- 2015
- VLSI Technology 2015
Strained-SiGe channel FinFETs for high-performance CMOS: Opportunities and challenges
- Pouya Hashemi
- Karthik Balakrishnan
- et al.
- 2015
- ECS Meeting 2015 Chicago
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
- X. Chen
- S. Samavedam
- et al.
- 2008
- VLSI Technology 2008