Challenges and opportunities for high performance 32 nm CMOS technology
- J. Sleight
- I. Lauer
- et al.
- 2006
- IEDM 2006
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188 results for Devendra Sadana
Amorphization/templated recrystallization (ATR) method for hybrid orientation substrates
- K.L. Saenger
- J.P. De Souza
- et al.
- 2006
- MRS Spring Meeting 2006
High performance CMOS bulk technology using direct silicon bond (DSB) mixed crystal orientation substrates
- Chun-Yung Sung
- Haizhou Yin
- et al.
- 2005
- IEDM 2005
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)
- J. Cai
- K. Rim
- et al.
- 2004
- IEDM 2004
Selectively formed high mobility strained Ge PMOSFETs for high performance CMOS
- Hulling Shang
- Jack O. Chu
- et al.
- 2004
- IEDM 2004
Performance enhancement on sub-70 nm strained silicon SOI MOSFETS on ultra-thin thermally mixed strained silicon/SiGe on insulator(TM-SGOI) substrate with raised S/D
- B.H. Lee
- A.C. Mocuta
- et al.
- 2002
- IEDM 2002
High performance 0.18 μm SOI CMOS technology
- E. Leobandung
- E. Barth
- et al.
- 1999
- IEDM 1999
0.25 μm CMOS SOI technology and its application to 4 Mb SRAM
- D. Schepis
- F. Assaderaghi
- et al.
- 1997
- IEDM 1997
Effect of the back gate conduction on 0.25 μm SOI devices
- J.L. Pelloie
- D.K. Sadana
- et al.
- 1994
- IEDM 1994
Enhanced short-channel effects in NMOSFETs due to boron redistribution induced by arsenic source and drain implant
- D.K. Sadana
- A. Acovic
- et al.
- 1992
- IEDM 1992