GaN-based high electron mobility transistors (HEMTs) were fabricated on 200-mm silicon-on-insulator (SOI) substrates possessing multiple crystal orientations. These SOI substrates have the Si (100)-SiO2-Si (111) structure, which allows Si (111) to be exposed below the buried oxide to enable GaN epitaxial growth adjacent to Si (100). The current collapse in GaN HEMTs of < 150 × 150 μm2 patterns is 2%-6%, which is remarkably lower than the devices on blanket materials. We believe that stress relaxation resulting from substrate patterning contributes to the reduction of current collapse. By creating small GaN patterns on a larger diameter Si wafer, co-integration of GaN with Si technology may be possible.