Publication
VLSI Technology 2017
Conference paper

High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length

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Abstract

We report the fabrication of short-channel FinFETs on InGaAs-on-silicon wafers using the aspect ratio trapping (ART) technique. We demonstrate excellent short-channel control down to 20 nm gate length due to scaled fin width down to 9 nm and reduction of parasitic bipolar effect (PBE). PBE that plagues III-V NFETs with gate-all-around (GAA) or III-V-on-insulator (III-V-OI) structures can be significantly suppressed by optimized ART FinFET technology. We demonstrate record high on-current ION and low drain leakage current for short gate lengths in the 20-32 nm range for InGaAs-on-silicon NFETs.

Date

31 Jul 2017

Publication

VLSI Technology 2017

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