Design and analysis of a self-repairing SRAM with on-chip monitor and compensation circuitry
- Niladri Narayan Mojumder
- Saibal Mukhopadhyay
- et al.
- 2008
- VTS 2008
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45 results for Kaushik Roy
An on-chip test structure and digital measurement method for statistical characterization of local random variability in a process
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs
- Jing Li
- Aditya Bansal
- et al.
- 2008
- ACM JETC
Optimal dual-VT design in sub-100 nanometer PDSOI and double-gate technologies
- Aditya Bansal
- Jae-Joon Kim
- et al.
- 2008
- VLSID 2008
Optimal dual-VT design in sub-100-nm PD/SOI and double-gate technologies
- Aditya Bansal
- Jae-Joon Kim
- et al.
- 2008
- IEEE Transactions on Electron Devices
A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nm CMOS
- Ik Joon Chang
- Jae-Joon Kim
- et al.
- 2008
- ISSCC 2008
High-performance device optimization and dual-VT technology options for doublegate FET
- Aditya Bansal
- Keunwoo Kim
- et al.
- 2007
- ICICDT 2007
Accurate modeling and analysis of currents in trapezoidal FinFET devices
- R.M. Rao
- A. Bansal
- et al.
- 2007
- SOI 2007
Poly-Si thin-film transistors: An efficient and low-cost option for digital operation
- Jing Li
- Aditya Bansal
- et al.
- 2007
- IEEE Transactions on Electron Devices
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50 nm double gate devices
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2007
- Microelectronics Journal