Poly-Si thin-film transistors: An efficient and low-cost option for digital operation

Abstract

In this paper, we propose an optimization methodology to design low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) for submicrometer (L = 200 nm) ultralow-power digital operation. LTPS TFTs incur low fabrication cost and can be fabricated on a variety of substrates (flexible such as polymer, glass, etc.). LTPS TFT has significantly reduced mobility, resulting in reduced driving current; however, we show that, for ultralow-power subthreshold operation (Vdd < Vth), LTPS TFTs can be optimized to achieve comparable performance as a single-crystalline silicon (c-Si) silicon-on-insulator (SOI). For LTPS TFTs with TSi < 10 nm, ring oscillators (operating in subthreshold region) show significant reduction in intrinsic delay when the midgap trap density gets properly controlled (1012 cm-2 after hydrogenation with less dynamic energy consumption under isostatic power consumption compared to a c-Si SOI MOSFET. We also address the inherent variations in grain boundaries at device and circuit levels to gain practical insights. © 2007 IEEE.