Optimal dual-V_T design in sub-100 nanometer PDSOI and double-gate technologies

Abstract

Dual-VT CMOS is an effective way to reduce leakage power in high-performance VLSI circuits. In this paper, we explore the technology design space for dual-threshold voltage transistor design in deep sub-100nm technology nodes. We propose a technique of achieving high-VT devices - longer gate sidewall offset spacers to increase the channel length without increasing the printed gate length. Effectiveness of all the dual-VT technology options increasing channel doping, increasing gate length and proposed technique of increasing spacer thickness - are analyzed at transistor to basic logic gate level. Results indicate that the proposed technique yields lower dynamic power consumption and lower performance penalty compared with longer gate length and high body doping devices. Our proposed technique, however, incurs extra fabrication mask similar to high-VT by increasing body doping. © 2008 IEEE.