A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nm CMOS

Abstract

We demonstrate a 10T subthreshold SRAM with an efficient bit-interleaving structure for soft-error tolerance and a differential read scheme for improved stability. The 32kb (256×128) SRAM array is fabricated in 90nm CMOS and operates at 31.25kHz at 0.18V With more aggressive wordline boosting, the V DD can be reduced to 0.16V At the minimum VDD condition, the operating frequency is 500Hz and the power consumption is 0.123μW. ©2008 IEEE.