High-performance device optimization and dual-V_T technology options for doublegate FET

Abstract

In this paper we explore the technology design space for sub-45nm double-gate devices. Device geometry is optimized to achieve minimum gate delay (CV/I) under a leakage constraint. We show that the constraint on silicon thickness (to control short-channel-effect) can be relaxed by optimizing gate sidewall offset spacers (to control sourceldrain extension). Further, to reduce active leakage power in high-performance circuits, we explore technology options for dualthreshold voltage device design. We compare the effectiveness of higher body doping and longer channel length to obtain high-VT devices, and propose high-VT devices using dual-spacer thicknesses to vary channel length instead of increasing drawn gate length. Results indicate that the dual-spacer technique yields device/circuit performance comparable to body doping, while offering the advantage ofless process variability. ©2007 IEEE.