Efficiency attacks on spiking neural networks
- Sarada Krithivasan
- Sanchari Sen
- et al.
- 2022
- DAC 2022
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44 results for Kaushik Roy
A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nm CMOS
- Ik Joon Chang
- Jae-Joon Kim
- et al.
- 2008
- ISSCC 2008
Statistical characterization and on-chip measurement methods for local random variability of a process using sense-amplifier-based test structure
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2007
- ISSCC 2007
Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2006
- IEEE Electron Device Letters
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor
- Prithviraj Banerjee
- Joe T. Rahmeh
- et al.
- 1990
- IEEE TC
Using graphical models as explanations in deep neural networks
- Franck Le
- Mudhakar Srivatsa
- et al.
- 2019
- MASS 2019
Neural networks at the edge
- Deboleena Roy
- Gopalakrishnan Srinivasan
- et al.
- 2019
- SMARTCOMP 2019
Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal
- Karthik Yogendra
- Minsuk Koo
- et al.
- 2017
- NANOARCH 2017
Column-selection-enabled 8T SRAM array with 1R/1W multi-port operation for DVFS-enabled processors
- Sang Phill Park
- Soo Youn Kim
- et al.
- 2011
- ISLPED 2011
Double-Gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM
- Ashish Goel
- Sumeet Gupta
- et al.
- 2009
- DRC 2009