Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond
- Chung-Hsun Lin
- Wilfried Haensch
- et al.
- 2011
- VLSI Technology 2011
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27 results for Josephine B. Chang
A 0.021 μm2 trigate SRAM cell with aggressively scaled gate and contact pitch
- Michael A. Guillorn
- Josephine Chang
- et al.
- 2011
- VLSI Technology 2011
Full metal gate with borderless contact for 14 nm and beyond
- Soon-Cheon Seo
- L.F. Edge
- et al.
- 2011
- VLSI Technology 2011
Non-planar device architecture for 15nm node: FinFET or trigate?
- Chung-Hsun Lin
- Josephine Chang
- et al.
- 2010
- IEEE International SOI Conference 2010
Wafer scale fabrication of carbon nanotube FETs with embedded poly-gates
- Shu-Jen Han
- Josephine Chang
- et al.
- 2010
- IEDM 2010
Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm
- Sarunya Bangsaruntip
- A. Majumdar
- et al.
- 2010
- VLSI Technology 2010
Gate-all-around silicon nanowire MOSFETs and circuits
- Jeffrey W. Sleight
- Sarunya Bangsaruntip
- et al.
- 2010
- DRC 2010
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2010
- ISSCC 2010
Hydrogen silsesquioxane-based hybrid electron beam and optical lithography for high density circuit prototyping
- M. Guillorn
- J. Chang
- et al.
- 2009
- Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- H. Kawasaki
- V.S. Basker
- et al.
- 2009
- IEDM 2009