Next-Generation Logic Design Architecture for Vertical-Transport Nanosheets
- Biswanath (Biswa) Senapati
- Jeongho Do
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Invited talk
Publications
78 results for Huiming Bu
Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology
- Gen Tsutsui
- Seunghyun Song
- et al.
- 2022
- IEDM 2022
Invited talkGate-Last IO Transistors based on Stacked Gate-All-Around Nanosheet Architecture for Advanced Logic Technologies
- M. Bhuiyan
- M. Kim
- et al.
- 2021
- IEDM 2021
Conference paperCritical Elements for Next Generation High Performance Computing Nanosheet Technology
- R. Bao
- C. Durfee
- et al.
- 2021
- IEDM 2021
Conference paperVertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Conference paperHighly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors
- Curtis Durfee
- Subhadeep Kal
- et al.
- 2021
- ECS Meeting 2021
Conference paperChallenges and Opportunities for Stacked Transistor: DTCO and Device
- J. Wang
- S.D. Suk
- et al.
- 2021
- VLSI Technology 2021
Conference paperStacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel
- Shogo Mochizuki
- M. Bhuiyan
- et al.
- 2020
- IEDM 2020
Conference paperParasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors
- Su-Chen Fan
- Ruilong Xie
- et al.
- 2020
- IITC 2020
Conference paperSelective Enablement of Dual Dipoles for near Bandedge Multi-Vt Solution in High Performance FinFET and Nanosheet Technologies
- Ruqiang Bao
- K. Watanabe
- et al.
- 2020
- VLSI Technology 2020
Conference paper