Publications

78 results for Huiming Bu

Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
- - Nick Lanzillo
  - Jim Mazza
  - et al.
- 2025
- IEDM 2025
NanoStack Transistor Architecture for CMOS 7A Node and Beyond
- - S. Reboh
  - C. Zhang
  - et al.
- 2025
- VLSI Technology and Circuits 2025
Hot Carrier Degradation and performance boost on Si Channel nFET Gate-All-Around Nanosheet Devices
- - H. Zhou
  - M. Hasanuzzaman
  - et al.
- 2025
- IRPS 2025
Advanced Multi-Vt Enabled by Selective Layer Reductions for 2nm Nanosheet Technology and Beyond
- - Ruqiang Bao
  - Yusuke Oniki
  - et al.
- 2024
- IEDM 2024
Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
- - Chen Zhang
  - Seungmin Song
  - et al.
- 2024
- IEDM 2024
Fully subtractive Ru Topvia interconnects with minimum 9 nm-space airgap for RC performance and reliability enhancement as post-Cu interconnects
- - Koichi Motoyama
  - Jaemyung Choi
  - et al.
- 2024
- IEDM 2024
Backside power distribution for nanosheet technologies beyond 2nm
- - Ruilong Xie
  - Wonhyuk Hong
  - et al.
- 2024
- VLSI Technology and Circuits 2024
Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
- - Shogo Mochizuki
  - Nicolas Loubet
  - et al.
- 2023
- IEDM 2023
Vertical-Transport Nanosheet Technology for Scaling beyond the Lateral-Transport Devices CMOS Era
- - Hemanth Jagannathan
  - Susan Fan
  - et al.
- 2023
- SSDM 2023
The future transistors
- - Wei Cao
  - Huiming Bu
  - et al.
- 2023
- Nature