In this paper, we demonstrate a first of a kind SiGe dry etch technique for the formation of inner spacers and for channel release, enabling stacked NanoSheet (NS) gate-all-around device architectures. This novel etch involves a precisely controlled lateral SiGe etch with very high selectivity to Si. A detailed characterization of this novel process and its selectivity and tunability as a function of Ge concentration are discussed. The outstanding 150:1 selectivity for SiGe25% versus Si of this process makes it the best candidate for inner spacer shape and depth control, and enables a wide range of NS device widths on the same wafer with low Si channel thickness variability, which is critical for power/performance optimization of high performance computing stacked NS devices. As a result, very low transistor threshold voltage and subthreshold slope variations versus device width are measured. The reduced Si channel (sheet) thinning obtained with this etch process improves device performance over the standard etch method, as measured by drain current, max transconductance and bias-temperature instability.