3-D stacking of chiplets in Heterogeneous Integration (HI) packages with interconnects to supply power and transfer data is gaining popularity for High-Performance Computing (HPC) applications. Key advantages driving interest in this approach include vertical stacking which increases bandwidth and reduces energy and parasitic losses for high-power computing applications. However, chip stacking may increase the package height and increase the thermal and mechanical stresses on the package. Furthermore, compute intensive HPC applications like Artificial Intelligence (AI) and machine learning (ML) algorithms drive significant thermal management challenges. Therefore, it is critical to characterize the thermal performance of stacked silicon packages to predict the cooling requirements for optimal functioning in high-power computing applications. In this study, a numerical simulation model is built for a lidded 3-D package with a two-chip stack. The model is validated against experiments for a 2-D package architecture with a spreader. A comprehensive case study then is performed by applying different boundary conditions, changing physical parameters, and by making geometrical modifications, with the overall goal being to independently analyze the effects of each on thermal performance compared to that of a baseline case. The boundary conditions studied include variable uniform power map in one or both chips, non-uniform heat dissipation, and convection heat transfer coefficient of the spreader. The physical parameters include chip thickness, TIM material, and lid thickness. The geometrical modifications include logic chip on memory and vice-versa, face-to-face vs. face-to-back bonding, pitch of interconnect, number of chips in stack, and number of chiplets in a stack layer. Based on the thermal performance for these conditions, required cooling techniques are suggested for improved functioning of the overall 3-D assembly. Candidate approaches to reducing thermal resistance and package temperature are also prescribed.