Publication
IEDM 2019
Conference paper

Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applications

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Abstract

We report for the first time reliable 2 ns switching of spin-transfer torque magneto-resistive random access memory (STT-MRAM) devices by demonstrating 100% write-error-rate (WER) yield at 1e-6 write-error floor of 254 devices with tight distributions and steep WER slope at a nominal size of 49 nm. A single device was demonstrated with 2 ns write pulses to have less than 1e-11 write-error rate, limited only by test time. We further demonstrate reliable 3 ns switching performance, with 99% WER yield at 1e-6 write-error floor of 256 devices with nominal size of 43 nm and a single device with less than 1e-11 write-error rate with a completely different free layer materials design. These two different free layer materials designs address one of the major remaining challenges for STT-MRAM to replace SRAM for last level cache (LLC) applications.

Date

01 Dec 2019

Publication

IEDM 2019

Authors

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