Integration of high porosity low-k dielectrics faces major challenges as the porosity weakens the dielectric, resulting in severe plasma induced damage (PID) and difficulties in profile control. Post porosity plasma protection (P4) integration strategy addresses those challenges by strengthening the dielectric via porosity refill during the integration steps. Realization of P4 integration at an advanced node is nontrivial. In this paper, we demonstrate the feasibility of the P4 integration scheme in a dual damascene double patterning 48 nm pitch test vehicle with a plasma enhanced chemical vapor deposited (PECVD) k = 2.4 inter-layer dielectric (ILD). In addition, initial results of applying P4 with a PECVD k = 2.2 ILD show promise in reducing capacitance at 48 nm pitch and beyond.