In this work, we report for the first time the experimental evidence of layout dependence on gate dielectric time-dependent-dielectric-breakdown TDDB in a leading edge HKMG FinFET technology. Structures with identical total effective gate area but various Fin and finger configurations per unit cell show more than 10X difference in Tbd and Qbd before process optimization. Fin number per unit cell was found to be the major impact factor based on the correlation between Tbd and ToxGL extracted from initial leakage currents. The implication of these findings on technology qualification methodology is that one needs to evaluate layout sensitivity for processes under development to confirm that reliability assessment is valid for structures having various layout configurations. Processes with strong layout dependence should be optimized before technology qualification.