Publication
IEEE Electron Device Letters
Paper

# Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning

## Abstract

We demonstrate a novel process for building a Resistive RAM (ReRAM) stack which reduces the forming voltage ( $\text{V}-{\textit {form}}$ ) and increases the switching resistance, both characteristics that are important ingredients for the use of ReRAM in scalable analog compute for AI. Utilizing this process, we explore analog switching characteristics above 100k $\Omega$ and demonstrate 4-bit programming at Rmax $=1\text{M}\Omega$. Utilizing the same writing characteristics, CIFAR-10 inference simulation shows 90% accuracy, comparable to the full precision model accuracy.

01 May 2021

## Publication

IEEE Electron Device Letters