VLSI Technology 2009
Conference paper

Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain


A new integration scheme is presented to solve device and manufacturing issues for extremely thin SOI (ETSOI) technology with high-k/metal gate. Source/drain and extensions are effectively doped by an implant-free process to successfully reduce series resistance below 200Ω•μm. A zero-silicon-loss process is developed to eliminate loss of thin SOI layer during gate and spacer processes, enabling structural demonstration of sub-2nm ETSOI. Even without strain boosters, a remarkable PFET drive current of 550μ A/μ m is achieved at Ioff = 3nA/μm, VDD = 0.9V with 6nm SOI channel and 25nm physical gate length. Short-channel effects are well-controlled with DIBL less than 100mV/V and subthreshold swing less than 90mV/dec. A 15% reduction in parasitic capacitance is achieved by a faceted raised source/drain (RSD). Excellent electrostatics and small device dimensions render ETSOI devices suitable for 22-nm node and beyond.