Scaling opportunities for Gate-All-Around: A patterning perspective
- I. Seshadri
- E. Miller
- et al.
- 2023
- IEDM 2023
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20 results for Indira Seshadri
Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
Overlay Performance in Permanent Bonded Wafer Integration Schemes
- Nathan Ip
- Michael Belyansky
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Challenges and Opportunities for Stacked Transistor: DTCO and Device
- J. Wang
- S.D. Suk
- et al.
- 2021
- VLSI Technology 2021
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
- A. Greene
- Huimei Zhou
- et al.
- 2019
- VLSI Technology 2019
On thermal interface materials with polydisperse fillers: Packing algorithm and effective properties
- Piyas Chowdhury
- Anuja De Silva
- et al.
- 2018
- InterPACK 2018
Polymer brush as adhesion promoter for EUV patterning
- Jing Guo
- Anuja De Silva
- et al.
- 2018
- SPIE Advanced Lithography 2018
Development of amorphous silicon based EUV hardmasks through physical vapor deposition
- Anuja De Silva
- Yann Mignot
- et al.
- 2017
- SPIE Photomask Technology + EUV Lithography 2017
Reliable airgap BEOL technology in advanced 48 nm pitch copper/ULK interconnects for substantial power and performance benefits
- C. J. Penny
- S. Gates
- et al.
- 2017
- IITC 2017