A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor

Abstract

A per-core clock generator for the eight-core POWER7™ processor is implemented with a digital PLL. This frequency generator is capable of smooth, controlled frequency slewing, minimizing the impact of di/dt. Frequency can be dynamically adjusted while the clock is running, and without skipping any cycles, thus enabling aggressive power management techniques. © 2010 IEEE.