Conference paper
CMOS integrated silicon nanophotonics for exascale computing
William M. J. Green, Solomon Assefa, et al.
FiO 2011
A static frequency divider designed in a 210-GHz fT, 0.13-μm SiGe bipolar technology is reported. At a -5.5-V power supply, the circuit consumes 44 mA per latch (140 mA total for the chip, with input-output stages). With single-ended sine wave clock input, the divider is operational from 7.5 to 91.6 GHz. Differential clocking under the same conditions extends the frequency range to 96.6 GHz. At -5.0 V and 100 mA total current (28 mA per latch), the divider operates from 2 to 85.2 GHz (single-ended sine wave input).
William M. J. Green, Solomon Assefa, et al.
FiO 2011
Thomas Zwick, Christian Baks, et al.
AP-S/URSI 2004
Ullrich R. Pfeiffer, Arun Chandrasekhar, et al.
IEEE-SPI 2004
Mark Ferriss, Alexander Rylyakov, et al.
VLSI Circuits 2013