About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
ISSCC 2007
Conference paper
A 7Gb/s 9.3mW 2-Tap current-integrating DFE receiver
Abstract
A 7Gb/s 2-tap current-integrating DFE implemented in a 90nm CMOS process is presented. Low power dissipation (9.3mW) is achieved by replacing resistively loaded analog current summers with resettable integrators. With 7Gb/s PRBS-7 data, the input sensitivity is 61mVpp-diff, and the DFE equalizes a 16-inch backplane with 45% horizontal eye opening. The DFE core (integrators, latches, clock buffers) occupies 85×65μm2. ©2007 IEEE.