Publication
ISSCC 2019
Conference paper

6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET

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Abstract

The growing demand for higher data rates in wireline communications has led to emerging standards in the 100Gb/s+ range using PAM-4 signaling. ADC-based receivers have demonstrated robust operation over channels with high losses (>20 dB) [1], but their power consumption (>500 mW/lane excluding DSP) is prohibitive for applications requiring large port counts in short-reach chip-to-chip and chip-to-module links (such as OIF-CEI-112G-VSR/XSR/USR). This work demonstrates a dual PAM-4/NRZ RX implemented in 14nm FinFET and measured up to 100Gb/s in PAM-4 mode achieving pre-FEC BER < 10{-12} across a 19.2dB-loss channel with low power. To achieve low BER with >16 dB loss channel the RX uses a CTLE combined with a 1-tap speculative DFE. To minimize power consumption, the number of slicing levels to resolve the 1-tap PAM-4 DFE speculation is reduced from 12 to 8 by shaping the channel to a1 +0.5D response (h 0 +0.5 ast h0) with CTLE and TXFFE. With a1 +0.5D channel, 4 out of 12 speculative decisions are overlapped. Moreover, comparators used for DFE speculation can be shared for phase detection in a baud-rate CDR scheme, extending the concept proposed in [2] to PAM-4. In NRZ mode, the RX features a fully speculative 3-tap DFE to equalize high loss channels (>35 dB) at 56Gb/s. The RX incorporates the following key advances: (1) a trans-admittance trans-impedance (TAS-TIS) CTLE circuit resulting in a low-power and compact analog-front-end (AFE), (2) a 1-tap PAM-4 speculative DFE based on a1 +0.5D response, and (3) a CMOS quadrature-DLL (QDLL) generating quadrature clock phases resulting in a low jitter/power clock path.

Date

06 Mar 2019

Publication

ISSCC 2019

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