A DDR4 transmitter (TX) for direct-attach memory on a processor chip is presented as well as the design of the associated low-dropout linear voltage regulators (LDO) that generate the split-mode supply voltages for the thin-oxide protection of the TX output stages operated from the 1.2 V DDR4-supply. The TX uses AC-boost equalization. Signal-integrity (SI) simulations have shown that pre-emphasis equalization is better suited to meet the DRAM eye mask specification than de-emphasis equalization. The LDO design is optimized for good frequency compensation at large load variations, which typically occur during burst-mode transmissions in DDR memory links. A wide-band low-output impedance buffer located between the LDO's error amplifier and the power transistor is proposed that implements a load-sensing and current-injection scheme to extend the low-output impedance range of the buffer, which in turn stabilizes the dominant output pole over a wider di/dt-range. The design is implemented in 14-nm silicon-on-insulator (SOI) CMOS technology, and the key performance measures are 2.8 pJ/b efficiency of the TX when driving with 34 Ω into a 40 Ω DRAM load and a figure-of-merit (FOM) of 96 ps for the LDO.