SSDM 2023
Invited talk

Vertical-Transport Nanosheet Technology for Scaling beyond the Lateral-Transport Devices CMOS Era

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Vertical-Transport (VTFET) Nanosheet Technology is a revolutionary device architecture that explores the “Z” dimension of space to overcome many challenges faced by conventional Lateral-Transport technology. This novel device architecture ushers in a new era of sub-45nm contacted gate pitch (CGP) CMOS technology with superior performance over scaled FinFETs. VTFETs maintain good electrostatics, low effective capacitance (Ceff), and low parasitics compared to scaled FinFETs that are severely impacted by scaling constraints. Novel technology elements such as Zero Diffusion Break, self-aligned gate formation, simplified middle-of-line (MOL) contacts among others are enabled through VTFETs providing additional advantages over leading-edge competitive Lateral-Transport technology.